1. Field of the Invention
The present invention relates generally to a frequency synthesizer, and more particularly pertains to a particular type of frequency synthesizer, specifically one which consists of n identical modules, each of which generates one digit of the final frequency number in hertz, in which a phaselock loop is utilized in such a manner therein as to simplify the synthesizer and to make it less expensive.
2. Discussion of the Prior Art
The precise determination and control of frequencies is increasingly important and necessary in the present continually expanding and improving electronics industry. Stability of operational frequency standards has improved from about 10.sup.-4 in tuning fork types to one part in 10.sup.10 or 10.sup.11 now available with crystal, atomic and molecular frequency sources. Recently developed techniques for long range synchronization employing pulse timing and very low frequency phase comparison allow intercomparison of remote frequency reference sources on a world-wide basis to within a few parts in 10.sup.10.
Precision frequency references are inherently fixed frequency or very narrow band devices. However, operational electronic systems operate at frequencies that span the entire spectrum, and additionally often have to be variable over wide ranges of frequency with stable frequency operation. Moreover in most electronic systems, periodic checking of a variable local oscillator no longer provides a sufficient degree of control. The frequency synthesizer has been developed to fulfill these requirements, and usually by a series of arithmetical operations converts one or more reference frequencies to the desired frequency.
Primary difficulties encountered in the development of satisfactory frequency synthesizers include: attenuation to acceptable levels of unwanted side-bands and modulation components generated in the synthesizer circuits; production of controllable small increments of frequency without generation of difficult-to-filter side-bands; provision for very rapid frequency switching; assurance of a very high degree of inherent reliability; and often the circuits utilized many relatively expensive components such as crystal filters.
Phase locked loops (PLL) are also well known in the art, and have often been implemented in frequency synthesizers. However, phase locked loop oscillators were often intentionally not utilized in the prior art in order to be able to generate very pure signals and to achieve high speed switching from one frequency to another in about 200 usec.
A particular prior art frequency synthesizer of interest employs n identical digital modules, each of which generates one digit of the final frequency number of the frequency of the synthesized output signal. Each digit module has ten reference frequencies available to it. This type of frequency synthesizer can comprise any number of digit modules, depending generally upon the number of digits in the synthesized frequency output signal. U.S. patents to Muraszko U.S. Pat. No. 3,202,930, Dimmick, U.S. Pat. No. 3,227,963, Noyes, Jr., U.S. Pat. No. 3,300,731, and Connell, et al. U.S. Pat. No. 4,395,683 each disclose this same general type of frequency synthesizer having n identical digit modules, each having a PLL therein, and each is distinguishable from the present invention as each digit module therein requires ten input reference frequencies available for selection, rather than one reference frequency and a controlled divide-by-n counter, as in the present invention.
Orenberg U.S. Pat. No. 3,600,699 is of particular interest to the present invention as disclosing a similar type of frequency synthesizer which is pertinent thereto. In this reference, each digit module generates a particular frequency by one reference frequency and a digitally controlled divide-by-n counter. However, Orenberg is also quite different from the present invention as, in each digit module, the PLL combines the functions of both the first digit adder and the second digit adder in one very complex PLL. Thus, in Orenberg, a reference signal is mixed in a mixer with the output of a VCO, and the output of the mixer is filtered to obtain only the difference frequency, which is directed to a variable divide-by-n counter, and the phase of the resultant signal is compared in a phase comparator with the phase of a second input reference signal. The output of the phase comparator is filtered, and then drives the VCO to the proper frequency for that digit module. In contrast therewith, the present invention proposes to replace only the first digit adder with a PLL, and the second digit adder (with its mixer, filter and input second reference frequency) remains as a separate circuit, which is not a part of the much simpler PLL.